UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 71877

UltraScale+ PCI Express Integrated Block (Vivado 2018.3) - Reconfigurable Stage 2 support for Tandem PCIe w/ Field Updates

Description

Version Found:

  • DMA / Bridge Subsystem for PCI Express v4.1 (Rev. 2) - (Vivado 2018.3)
  • UltraScale+ PCI Express Integrated Block v1.3 (Rev. 4) - (Vivado 2018.3)

Version Resolved and other Known Issues: DMA Subsystem for PCI Express (Xilinx Answer 65443) / UltraScale+ PCI Express Integrated Block (Xilinx Answer 65751)

(PG213) The UltraScale+ PCI Express Integrated Block Product Guide mentions "Reconfigurable Stage Twos".

"Essentially with Reconfigurable Stage Twos, stage 2 bitstreams can act as partial bitstreams, and therefore they are interchangeable when paired with a fixed stage 1 bitstream."

In UltraScale devices, there was a restriction that the stage 2 bitstream used to complete the initial configuration must come from the same checkpoint that generated the stage 1 bitstream.

The Product Guide states that this restriction no longer applies in UltraScale+ devices. However, due to an issue that has been detected in Vivado 2018.3 with UltraScale+ devices, "Reconfigurable Stage Twos" are no longer supported in UltraScale+ devices. This means the restriction which existed for UltraScale device also continues to apply to UltraScale+ devices.

Solution

The issue is scheduled to be fixed in a future release of the core.

For the Tandem PCIe with Field Updates flow with UltraScale+ devices in Vivado 2018.3, the stage 2 bitstream that is used to complete the initial configuration must come from the same checkpoint that generated the stage 1 bitstream. 

Then for the dynamic updates, do NOT use the stage 2 bitstreams, but instead use the partial bitstreams. 

 

Creation of partial bitstreams can be set in the design_field_updates.tcl script as shown below:

Original:

set updateVer1BitstreamsResult [genBitForTandemFieldUpdate $updateVer1Name {TandemPCIe}]

Updated Version:

set updateVer1BitstreamsResult [genBitForTandemFieldUpdate $updateVer1Name {TandemPCIe PR}]

This will generate both tandem stage1 and stage2 files along with PR bitfiles for version 1.

Original:

set updateVer2BitstreamsResult [genBitForTandemFieldUpdate $updateVer2Name {TandemPCIe}]

Updated Version:

set updateVer2BitstreamsResult [genBitForTandemFieldUpdate $updateVer2Name {PR}]

This will generate PR bitfiles for Stage2 and not Tandem Bitfiles for version 2.

These partial bitstreams will reconfigure only the update region, not the XDMA region (if that core is used). 

Reconfigurable stage 2 bitstreams include the XDMA part of the IP core, whereas the partial bitstreams for the users dynamic region do not.

Revision History:

03/01/2019 - Initial Release

Linked Answer Records

Master Answer Records

AR# 71877
Date 03/01/2019
Status Active
Type Known Issues
Devices More Less
Tools
IP
Page Bookmarked