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AR# 72060

UltraScale+ Integrated Block for PCI Express (Vivado 2018.3) - MSI-X Internal Table access can cause Completion To Time Out in Gen3 x16 Configuration

Description

Version Found: v1.3 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

 

When issuing consecutive reads on the MSI-X internal vector table, some of the read requests might get lost, causing completion timeout.

The host system will hang because of this. 

The issue occurs only in Gen3x16 configuration, other configurations do not have the stated issue.

A work-around for this issue for designs that use PF was previously documented in (Xilinx Answer 70952).

This has now been fixed in the patch attached to this Answer Record. The attached patch contains fixes for both PF and VF.

Note: (Xilinx Answer 70952) has been made obsolete.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

This issue is due to be fixed in a future version of the core.

The patch attached to this Answer Records contains a "readme" file which includes installation instructions.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

04/08/2019 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR72060_Vivado_2018_3_preliminary_rev1.zip 1 MB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
65751 UltraScale+ PCI Express Integrated Block - Release Notes and Known Issue N/A N/A
AR# 72060
Date 09/03/2019
Status Active
Type Known Issues
IP
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