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AR# 72175

Xilinx PCI Express IP - Debug Questions for Link Training Issues

Description

When filing PCI Express Link training issues either to Xilinx Technical Support via a Service Request or in the Xilinx PCI Express forum, please provide answer to the questions listed in this answer record.

This will make it easier and quicker to debug and provide meaningful debug suggestions. Most of the questions in the list apply to all Xilinx PCI Express IPs.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

System Configuration:


  • Indicate what board you are using: is it a Xilinx Development Board or a Customer Board? If it is a Xilinx development board, please provide the board revision ID.
  • Indicate motherboard description:
    • What is the link partner? Is it a switch, or a PC? Who is the manufacturer of that switch or PC? - Which Chipset are you using?
  • Did the failure occur in Gen1, Gen2, and/or Gen3?
  • Did the failure occur as RP (Root Port) and/or EP (Endpoint)?
  • Describe the channel between the FPGA and the link partner, and estimated channel loss at desired link speed. 
  • Is there any passive hardware (Interposer for analyzer, retimer) in the path?
    • How is the Xilinx part connected to the system / link partner?
    • (Chip-to-chip on single board, add-in card, backplane, cabling)

Regression:


  • Did the issue occur in previous Vivado versions too? Do other link width configurations show similar behavior?
  • Have you tried with Gen1x1 configuration?
  • Do you have a different board that you could try on? If you do, do you see the same issue on that board?
  • Have you tried on a different machine?

Clocking:


  • Did the clock lock?
  • What is the clocking architecture? Synchronous or Asynchronous?
  • Is SSC enabled?
    • Have you checked by disabling SSC?
  • What frequency are you using for the reference clock?

Design Implementation:


  • Were there any implementation (synthesis, routing) errors?
  • Were there any timing errors?
  • Have all of the IP constraints been verified by comparing with the Example Design XDC file? 

Failing Behavior:


  • What is the frequency of the error? For example, does it happen immediately or after 1 hour?
  • Can the error be cleared? If cleared, does the error come back?
  • Is this failure observed on multiple parts?
  • Does failure occur immediately after reset?
  • Does failure occur immediately, after first rate change, after multiple rate changes?
  • How long after successful rate change does it fail?
  • Does the issue occur with the Example Design as well or only in your design?

Debug Capability:


  • Was a protocol link analyzer used? If so, provide protocol link analyzer captures with the details of your analysis of the captures.
  • Do you have a high-speed oscilloscope available, to probe clock / power / data lines?
  • Do you have a free-running clock available to the FPGA?  (A clock that is separate from the PCIe reference clock, and not tied to the PCIe reset)
  • Do you have the ability to insert a clean clock in place of the on-board reference clock? 
  • Have you captured an LTSSM graph by enabling the JTAG Debugger feature in the GUI?
  • Have you run Eye Scan by enabling the In-system IBERT feature in the GUI?

SI Debug Info:


  • Has it been confirmed whether Clock Jitter and Power Noise are within the specification?
  • Power integrity measurements
  • EFCLK jitter measurements
  • Channel loss data
  • Eye Scan plots
  • Confirm whether DFE, LPM or AutoRxEq are selected in the core configuration.

Revision History:

  • 04/11/2019 -  Initial Release
AR# 72175
Date 04/11/2019
Status Active
Type General Article
IP
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