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Quick Reference: Traditional Flow (Bare-Metal)

Step 1

System and Solution Planning
Review Versal™ product and system architecture Select target device Identify performance requirements Identify power requirements Identify I/O requirements Review and select PCI Express and Ethernet protocols Identify additional design requirements

Step 2

Individual design processes can be performed in parallel during step 2.

HW, IP and Platform Development	Embedded SW Development
Create Vivado® project Create top-level Vivado IP integrator block design including CIPS IP V* Define IO & GT placement, boot mode Add AXI IP to block design canvas, incl. AXI NOC V* Design IP in RTL or HLS Ensure design adheres to coding guidelines Assemble top-level design Constrain the design Run synthesis and methodology checks Simulate the design to validate functionality Review utilization and power against original budget Run design through Vivado implementation Iterate on design closure Perform memory performance tuning Review utilization and power against original budget Create programmable device image V* = New and required for Versal designs	Create Vitis™ project workspace Use New Platform Wizard -- select New Platform from hardware Use New Application Wizard to create Vitis application Build platform & application using Vitis GUI Package boot collateral
	Board System Design
	Evaluate device capabilites Perform schematic entry Lay out and simulate the board design Prototype, build, and test

Step 3

System Integration & Validation

Simulate the design for functionality and early performance assessment
Iterate on design timing and power closure
Generate programmable device image (includes PLM firmware) V*
Perform hardware functional testing
Validate performance in hardware

V* = New and required for Versal designs

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Traditional Flow - Bare Metal (DH208)

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