Resource Utilization for Video DisplayPort 1.4 RX Subsystem v2.1

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
MODE
PHY_DATA_WIDTH
BITS_PER_COLOR
LANE_COUNT
AUDIO_ENABLE
AUDIO_CHANNELS
AUX_IO_TYPE
HDCP_ENABLE
VIDEO_INTERFACE
PIXEL_MODE
Fixed clocks (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs MMCM PLL BUFGCE Speedfile Status
xczu9eg ffvb1156 -2 test_1__rx 0 2 8 1 0 0 0 0 1 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100 6029 5860 0 2 0 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -2 test_2__rx 0 2 8 4 1 2 0 0 0 4 m_aud_axis_aclk=25 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100 11898 11758 0 4 1 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -2 test_3__rx 0 2 8 1 1 4 0 1 0 1 hdcp_ext_clk=203 m_aud_axis_aclk=25 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100 17650 13141 0 5 1 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -2 test_4__rx 0 2 16 1 0 0 1 0 1 hdcp_ext_clk=203 m_axis_aclk_stream1=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100 16106 11487 0 5 0 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -2 test_5__rx 1 2 12 1 1 5 0 0 0 4 m_aud_axis_aclk=25 m_axis_aclk_stream1=300 m_axis_aclk_stream2=300 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100 20812 20374 0 10 1 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -2 test_6__rx 1 2 16 2 1 2 0 0 1 4 m_aud_axis_aclk=25 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100 20963 20052 0 0 1 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -2 test_7__rx 1 2 10 4 0 0 0 1 4 rx_lnk_clk=405 rx_vid_clk=300 s_axi_aclk=100 17694 16676 0 0 0 0 0 1 PRODUCTION 1.25 05-09-2019

COPYRIGHT

Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.