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High-Level Synthesis Flow on Zynq using Vivado HLS

Course Description This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS.
Level Introductory
Duration 2 Days
Who should attend? Professors who are familiar with Xilinx FPGA technology and wish to get up to speed with system design using high-level synthesis technique.
Pre-requisites
  • System level design experience using Xilinx FPGA
  • Basic experience with Xilinx Vivado design software suite
  • Good understanding of C programming

Skills Gained

After completing this workshop, you will be able to:

  • Understand high-level synthesis flow of Vivado HLS
  • Apply directives to optimize design performance 
  • Perform system-level integration of blocks generated by the Vivado HLS tool

Course Overview

Day 1:

  • Introduction to HLS
  • Using Vivado HLS
  • Lab 1: Creating Project and Understanding Reports
    • Experience a basic design flow of Vivado HLS and review generated output.
  • Improving Performance
  • Lab 2: Optimizing Performance through Pipelining
    • Use pipelining technique to improve performance.
  • Data Types

Day 2:

  • Optimizing for Area and Resources
  • Lab 3: Improving Area and Resource Utilization
    • Use directives to optimize resource sharing.
  • Handling Block- and Port-Level Protocols
  • Coding Considerations
  • Creating a Processor System
  • Lab 4: Designing an Audio System
    • Use IP-XACT export capability of Vivado HLS to generate an IP and integrate the generated core in an embedded system developed using IP Integrator.

Common to PYNQ-Z1 and PYNQ-Z2

Common to ZedBoard and ZYBO

ZedBoard

ZYBO

Common to ZedBoard and ZYBO

ZedBoard

ZYBO