Hardware emulation is the process of debugging and functional verification of the system in development. Comprehensive hardware functional verification is critical to reduce development cost and time-to-market. Emulation provides quick bring-up and quick turn-around time when processing design changes. Also, emulation provides high design accessibility and debug visibility so that ASIC designers can catch potential hardware failures before the tape out. As software complexity and cost are drastically increasing, early hardware verification is essential to lower risk and accelerate system development.
To maximize system performance and enable accelerated and predictable design cycles with emulators, Xilinx delivers the most comprehensive design methodology and design development platform. The Vivado® Design Suite has delivered state-of-art development experience to emulation-class system designers. This is Xilinx’s 3rd generation of emulation-class tools, IP, and design flows.
For emulation platforms, Xilinx solutions :
With the Virtex®-7 2000T FPGA and the Virtex UltraScale™ VU440 FPGA, Xilinx has been the market leader for the highest capacity FPGAs. The 16nm Virtex UltraScale+™ family now includes the world’s largest FPGA, the Virtex UltraScale+ VU19P FPGA, achieving three consecutive generations of high-end leadership.
Built with ASIC emulation in mind
Extending device density lead to 4X at 20nm
Industry’s highest capacity FPGA
Breakthrough performance and integration for ASIC prototyping and emulation can be realized with Xilinx UltraScale™ architecture. Virtex® UltraScale devices simplify design partitioning through high logic capacity, over 90% device utilization, ASIC-like clocking, enhanced routing, and high-speed transceivers for pin multiplexing. This breakthrough architecture coupled with Xilinx’s Vivado® Design Suite provides the ideal solution for tackling the demands of leading-edge ASIC and SoC platforms.