Traditional and Desktop Prototyping
Enabling early software integration and firmware development prior to ASIC or SoC availability
FPGA-based prototyping is the process of debugging, verifying, and validating part or all of a system on one or more adaptive SoCs or FPGAs. FPGA-assisted prototyping reduces time to market by enabling hardware and software co-validation before physical parts are available.
AMD delivers the industry’s largest capacity adaptive SoC and FPGA1 with improved I/O and transceiver latency to maximize system performance. The AMD Vivado™ ML design suite delivers a state-of-the-art development experience with new implementation features designed to improve compile time and QoR. The AMD Versal™ Premium VP1902 adaptive SoC is the first emulation-class device to feature a scalar processing subsystem on-chip, which enables a wide range of control and stimulus generation use modes for SW/HW firmware development and system bring-up.
AMD offers significant advantages for developing FPGA-based prototyping systems:
- High-performance adaptive SoCs and FPGAs for faster verification of targeted designs
- An on-chip processing subsystem to extend the possibilities of SW/HW co-development
- Flexible and performant I/O to create a contiguous device
- Advanced debug solutions, including high-speed debug over PCIe® and re-entrant probe modification to reduce compile
- Flexible I/O and logic and an extensive IP ecosystem to emulate at-speed peripheral stimulus
Featured Adaptive Computing Partners
Documentation
Breakthrough performance and integration for traditional and desktop prototyping can be realized with the AMD Versal™ Premium VP1902 adaptive SoC. The VP1902 device doubles device capacity2 compared to the Virtex™ UltraScale+™ VU19P device in order to fit larger IP and design subsystems. The on-chip A72 Arm® processor enables a wide variety of prototyping use cases for software and hardware co-development. Our XPIO and MIPI D-PHY enable a wide variety of at-speed peripheral stimulus. These silicon features combine to provide an ideal solution for tackling the prototyping demands of cutting-edge ASIC, IP, and SoC development.
Ideal Target for ASIC, SoC, and IP Prototyping
On-chip dual-core Arm A-72 and dual-core R5 processors for HW/SW co-development
Extensive IP ecosystem for integrating at-speed peripheral stimulus
Integrated hard blocks to save power and resource utilization
Solution Summary and Benefits
- World’s largest logic capacity adaptive SoC1
- Reduces the number of partitions and simplifies board layout
- Enables 2X larger platform capacity2
- Enables 2X higher system performance3
- Vivado™ ML implementation tools
- Reduces compile time
- Improves QoR
- ASIC-like clocking efficiently maps complex ASIC and SoC clock trees
- High-bandwidth and low-latency I/O and transceivers
- Efficient pin multiplexing between adaptive SoCs
- Reduces latency across partitions for improved system performance
- Industry support with our High-Speed Transceiver Pin Multiplexing IP
- Debug Solutions
- Full debug visibility supporting configuration-based readback, writeback, and state capture
- High-speed debug over PCIe®
- Deep storage ILA to offload capture data to external memory
- Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus the Intel Stratix 10 GX 10M FPGA. (VER-002)
- Based on AMD internal analysis in May 2023, comparing the number of system logic cells of the Versal Premium VP1902 device versus the Virtex UltraScale+ VU19P device. (VER-001)
- Based on AMD internal system clock performance analysis in May 2023, comparing the Versal Premium VP1902 device to the Virtex UltraScale+ VU19P device across a range of design sizes and cut nets. (VER-006)
