The ability to control system failure modes through fault-tolerant design requires an implementation methodology that ensures fault propagation can be controlled. Xilinx Isolation Design Flow (IDF) provides fault containment at the FPGA module level, enabling single-chip fault tolerance by various techniques including:
IDF, pioneered for government cryptographic systems, is also appropriate for avionics, functional safety-related electronics, industrial robotics, critical infrastructure, financial systems, and other high-assurance, high-availability, and high-reliability systems. The IDF is part of a spectrum of reliability technologies that when appropriately combined provide unmatched reliability, performance, and cost effectiveness.
In addition to its long heritage serving government grade cryptographic systems, the IDF is an integral part of the Xilinx IEC61508 (Industrial Functional Safety) certified tool chain. Additionally, it can aid in meeting the requirements of the ISO26262 specification (Automotive Functional Safety).
* Only 7S50
The IDF is a methodology based on existing implementation tool flows (ISE design tools in this case). Additional time spent floor-planning the design is done using existing constraint tools (PlanAhead / Vivado GUI). Verification of work products (pinout and routed design) are done with a separate and independent tool (either IVT or VIV for ISE or Vivado respectively).
ISE Design Suite
Vivado Design Suite
Vivado Design Suite
IDF Verification tools (IVT and VIV) verify that an FPGA design partitioned into isolated regions meet the stringent standards for fail-safe design. IVT and VIV are used at two stages in the FPGA design cycle. They are used first, early in the flow, to perform a series of design rule checks on floorplans and pin assignments. After the design is complete, they are used again to validate that the required isolation is built into the design.
Isolation Verification Tool (IVT) for ISE Design Suite
IVT is an executable that runs outside of ISE but fully within the ISE environment. IVT runs as a set of Design Rule Checks (DRCs) required to prove the design being operated on is isolated. It outputs a graphical display of the design and a verbose text report.
Note that the current version of IVT supports Virtex-5, Spartan-6, and the 7-series family of FPGAs and SoCs.
Vivado Isolation Verifier (VIV) for Vivado Design Suite
VIV is Tcl based script that integrates with Vivado DRC engine. It is essentially a series of DRCs that are loaded into Vivado that perform all the checks required to prove a design is isolated. Unlike IVT, its ISE predecessor, VIV integrates into the development tool leveraging the user friendliness of the Vivado GUI but still maintaining an independent development path. Its output is integrated into the Vivado DRC GUI display as well as a text output as enabled by the Vivado DRC engine.
Note that the current version of VIV supports the 7-seires family of FPGAs and SoCs in Vivadio 2015.1 and beyond.
NOTE: Starting 2018.2 Vivado Isolation Verifier is integrated with Vivado Design Suite release and this support UltraScale+ devices (including Zynq UltraScale+). For more information refer to UG1291: Vivado Isolation Verifier User Guide.