Edge. Access. Metro. Core. No matter the network, security plays a vital role. Encryption and decryption must be built into every piece of the chain, from the link layer to the application itself—each with distinct protocols that are in constant evolution. Our broad range of solutions protects you against known and unknown threats. That’s because you can implement security directly within Xilinx programmable logic—and iterate as standards evolve and threats emerge.
Xilinx security solutions span line rates from 100M to 400G, crypto protocols, various packet processing and lookup requirements—even predictive malware detection built on machine learning algorithms. Your system is protected in the present—and future-proofed.
UltraScale+™ FPGAs provide the capability to encrypt up to nx1G - nx100G frames of payload via bulk crypto for the protocols used in Metro and Core optical nodes and switches. Versal™ ACAPs integrate AES-GCM-128/256 encryption/decryption functionality via the High-Speed Crypto (HSC) block to reduce power, simplify place/route times, and provide enough throughput for up to 400G per block.
IP is available today to scale from 1M to 400G of throughput, with addional flexibility via channelization. Versal’s HSC block provides up to 400G of integrated MACSec functionality with nx100G granularity, and up to 4k+ security associations (SAs). The Cipher Suites supported are AES-GCM-128/256 and AES-GCM-XPN-128/256 with configurable confidentiality/encryption offset.
Soft IP for Bulk Crypto and MACSec
1k+ Security Associations
Can be used in OTN, MACSec, IPSec, and higher-layer TLS encryption
400G Bulk Crypto with AES-GCM 128/256
4x100G, 2x200G or 1x400G
128 SAs per 100G of Crypto
Can be used in OTN, MACSec, IPSec, and higher-layer encryption
Xilinx FPGA and ACAP solutions offer high-performance inline IPSec processing where performance is needed most. Xilinx architectures deliver line-rate throughput with minimal latency without taxing the CPU.
Xilinx solutions implement and manage the IPSec data plane, including both IP and IPSec layer packet processing. Processing of packets for extraction of layer 2 and layer 3 fields at different throughputs is readily implemented in Xilinx FPGA and ACAP devices. IP solutions are available to implement: 1Gb/s to 400Gb/s, with deterministic latency. Security association (SA) and security policy (SP) lookups are easily implemented, and support 100’s to 10,000’s of lookups via Xilinx content-addressable memory (CAM) IP and high-bandwidth memory (HBM) FPGAs.
The flexibility of memory and packet processing available in Xilinx security IP makes it the only solution that can address server, router and access router in a single vender. A fixed solution cannot support a varying number of L3 VPNs or provide the level of search performance that can be achieved with Xilinx FPGAs and ACAPs. The range of encryption protocols supported by Xilinx includes:
1G-100G Inline IPSec
URAM for SA lookup and storage
Up to 100G Inline processing
Support for All protocols and IPSec modes
Xilinx CAM IP for lookup
1G-200G Inline IPSec
HBM for packet buffer and lookups
10,000+ Security Associations and policy
Xilinx HBM BCAM IP for lookup
58G SerDes for network connectivity
Configuration for replay protection window size
Multi-protocol support with tunnel and transport mode
Nx400 High-speed Crypto
Hardened Gen5 PCIe core
Hardened packet processing
End-to-end offload and acceleration frees up valuable resources without sacrificing security between users and applications, and clients and servers. Xilinx offers solutions from established protocols to cutting-edge machine learning for malware detection.
10-30x performance vs. CPU with security acceleration/offload.
20-30x when Xilinx used for parallel analysis of regular expressions.
A malware system that learns through artificial intelligence and is smart enough to identify new threats--even ones you may not have anticipated.
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