The Alveo™ U45N network accelerator is an FPGA-based platform that delivers low-latency, 2x100G line rate performance for infrastructure workloads in the data center—freeing up precious server CPU cycles from infrastructure tasks to run business-critical applications. Hyperscalers, cloud service providers, and telco operators can adapt to their own infrastructure requirements by customizing virtual switching (e.g., OVS), security workloads (e.g., IPsec) and storage protocols. When combined with the Vivado™ tool flow and a comprehensive OpenNIC reference-based design, the Alveo U45N card delivers the hardware platform, tools, and IP for FPGA developers to build and differentiate their own network acceleration solutions.
Hardware Acceleration at 2x100G Line Rate Performance
Adaptable for Custom and Evolving Workloads
Vivado™ Tools and Reference Design for Ease of Development
The Alveo™ U45N network accelerator is an open FPGA platform for accelerated offload in the data center. Developers can implement a range of applications and workloads for custom protocols, security policies, and computational storage via hardware implementation on FPGA fabric, tailored to their own infrastructure requirements. Below are a few examples.
Open vSwitch with Custom Packet Processing
Developers can design and implement Open vSwitch (OVS), permitting offloading of frame and packet processing from the host CPU onto the Alveo U45N accelerator card. Developers can implement standard overlays like VXLAN and Geneve or integrate their own features for packet frame encapsulation, monitoring, management, and more.
Virtual Firewall for Custom Security Policies
With the Alveo U45N platform, designers can integrate their own IP to help secure internal servers, VMs, containers, and client services from external threats. Developers can accelerate IPsec and other workloads to implement stateful firewall, stateless firewall, flow tracking, connection tracking, and more.
Storage Offload: NVMe-oF, NVMe/TCP
For next-generation storage systems, the Alveo U45N can be an ideal solution to develop NVMe over Fabric (NVMe-oF) or over TCP/IP (NVMe/TCP) applications. As an open FPGA platform, the Alveo U45N network accelerator can support custom packet headers and custom congestion control, improving overall throughput and latency. The FPGA fabric also provides the flexibility to accelerate a variety of storage workloads including data compression, encryption, deduplication, and virtualization while optimizing overall storage utilization.
For a full product overview, refer to the Product Brief.
|Board Specifications||Alveo U45N Network Accelerator|
|Electrical Power & Thermal||
1: Arm processor only supported using AMD OpenNIC reference design
AMD provides a comprehensive open source NIC reference design—OpenNIC—to simplify FPGA development of inline networking applications in the data center. Supported on various Alveo adaptable accelerator cards including the Alveo U45N network accelerator, OpenNIC is organized around the concepts of "shell" and "role", where the shell provides a standard set of hardware IP blocks for external interfaces, and the role allows for integration of custom IP. The opensource reference design includes
OpenNIC is available now as open source on GitHub.
The U45N Alveo Data Center accelerator card supports Vivado design entry. The Vivado flow is recommended for FPGA designers that want to use traditional design flows, such as RTL or HLx. Use the tabs below to get started with Vivado, and to download Xbflash2 Utilities.
For development using RTL and HLx, follow these steps:
|RHEL/CentOS 7.8, 7.9||xrt_202126.96.36.1996_7.8.2003-x86_64-xbflash2.rpm (zip)|
|RHEL 8.1, 8.2, 8.3, 8.4, 8.5||xrt_202188.8.131.526_8.1.1911-x86_64-xbflash2.rpm (zip)|
|Ubuntu 18.04.4 LTS, 18.04.5 LTS||xrt_202184.108.40.2066_18.04-amd64-xbflash2.deb|
|Ubuntu 20.04 LTS, 20.04.1 LTS, 20.04.2 LTS, 20.04.3 LTS||xrt_202220.127.116.116_20.04-amd64-xbflash2.deb|