Device Support

The following production devices are enabled in this release:

• Space-Grade Kintex UltraScale:- XQRKU060
• XA Kintex-7:- XA7K160T
• Virtex UltraScale+ HBM (-3):- XCVU31P, XCVU33P, XCVU35P, XCVU37P

Vivado Tools

• General

  • Support for command-line based Web Installer has been added that enhances user experience and productivity for installing Xilinx tools
  • Disk usage optimization enabled to reduce install footprint of Vivado tool
  • Xilinx has discontinued offering DVDs for Vivado tool
    
    

• System Generator for DSP

  • 2 New Super-Sample Rate (SSR) Blocks:Vector Assert and Vector Relational blocks added to the Xilinx SSR Block Library for building Super-Sample Rate (SSR) Designs for Xilinx devices, including the Zynq UltraScale+ RFSoC parts. Please refer to the User Guide for more information on Super-Sample Rate designs and the new block library.
  • Supported MATLAB Versions:R2018a, R2018b and R2019
    
    

• Vivado High Level Synthesis

  • C functions can be tagged as black-boxes, replaced by equivalent RTL modules supplied by the user
  • The scope of dataflow applicability can now be extended to support multiple readers of an array through the new “stable” pragma/directive
  • A sequence of dataflow ping-pong buffers can be specified through the stream pragma/directive to improve parallel execution
  • Modified resource pragma/directive for memory allows to specify storage type and latency
  • User can set ap_ctrl_none scoped to a dataflow region to improve throughput
  • C libraries
    • C++ templated super sample rate (SSR) FFT function. Systolic architecture supporting multiple data samples (integer or fixed point) at each clock cycle
    • Enhanced OpenCV support through xfOpenCV (release notes)
    • The full set of math.h functions is now natively optimized for fixed point data types
      
      

• RTL Synthesis

  • Added VHDL-2008 features including generics in packages, generic types in entities, and functions in generics.
  • Incremental Synthesis now available, with optional auto-incremental mode for Vivado projects.
    
    

• Model Composer

  • DSP Block Library: New FFT, IFFT and FIR blocks are now available to design and implement signal processing algorithms with Model Composer
  • Enhancements to Throughput Control: Expanded list of blocks supported for Throughput Control. Build designs with supported blocks and control the throughput requirements of the implementation without making any structural changes to the design
  • Additional Blocks that Support Streaming Data: Design and Implement algorithms with high-throughput requirements using an expanded set of blocks that support operations on streaming data. Examples: Look-up Table, Delay, Matrix Multiply, Submatrix etc.
  • Enhanced Complex Support in C/C++ Function Import: Added support for importing functions that use hls::x_complex types as well, in addition to std::complex, expanding the support for complex signals in custom blocks.
  • Enhancements to C/C++ Function Import: Create custom "Source" blocks for your design using the xmcImportFunction feature
  • Improved Support for Row-Matrix and Column-Matrix Signal Dimensions: Improvements to the code generation infrastructure to handle Row-Matrix [Nx1] and Column-Matrix [1xN] signals in the design, resulting in improved performance.
  • Supported MATLAB Versions: R2018a, R2018b and R2019a
    
    

• Interactive Design Environment

  • Automatically add new runs to the project summary dashboards
  • Ability to'Save As' for report strategies
    
    

• Board Flows and Example Designs

  • Download and install third party boards directly from Github with a single click in the GUI
     

• Vivado Simulator

  • Introducing support for SystemVerilog functional coverage and report generation(.txt or .html)
  • Support for assertion on property and sequence in concurrent region
  • Enhanced constraint randomization supportNew protocol instance window to display AXI interfaces in design
  • “Mark Simulation” feature in block diagram to add AXI interfaces in waveform viewer directly
     

• IP Security

  • Encrypted blocks in the design will be hidden in Schematic and Hierarchy viewer. New right xilinx_schematic_visibility has been introduced that can be toggled on/off to change the default behavior
  • Updated Xilinx Vivado public key as a part of regular security update
     

• Implementation

  • New AXI Regslice IPs to cross SLRs at high speed and automatically insert pipelines.
    • Improves Virtex UltraScale+ HBM design performance (up to 450 MHz).
    • Enabled for all UltraScale and UltraScale+ devices.
    • Property-based mechanism available for custom busses and interfaces.
  • Faster physical optimization of high-fanout nets during placement.
  • Automatic SLR crossing register usage is enabled to boost performance and reduce QoR variation
  • Report Methodology runs up to 2 times faster for designs with many timing exceptions.
  • opt_design adds an SRL remap option to convert between SRL shift register primitives and register chains. Allows balancing utilization and performance.
    
    

• Constraints and Analysis

  • Soft Pblocks: Pblock boundaries can be made soft to allow cells to move as needed to improve performance.
  • SLR Pblocks: Pblock ranges can now be specified using SLRs for much simpler definition.
  • The report_methodology command adds new timing-related methodology checks.
  • Suggestions from report_qor_suggestions (RQS) are now object-based and are automatically applied by implementation flow commands.
  • The report_ram_utilization command is rebuilt to provide more meaningful statistics on sparseness and timing criticality.
    
    

• Power Analysis

  • UltraScale+ XPE includes more detailed RF Data Converter settings for power analysis of Zynq UltraScale+ RFSoC Gen 3 devices.
  • UltraScale+ XPE adds an HBM wizard for system-level parameter entry for HBM power analysis, automatically generating the corresponding spreadsheet entries.
    
    

• Vivado Debug

  • IBERT GTM: GTM transceivers line rates of 9.8 Gb/s up to 58 Gb/s using PAM4 and NRZ modulations are now supported in IBERT design for GTM and Serial I/O Analyzer. Forward Error Correction (FEC) mode with PAM4 signaling is provided in 160-bit data width mode and internal PRBS patterns (no FEC support for NRZ). In addition,new plotting features are offered for eye slicers, histograms, and signal-to-noise ratio information of different links.
    
  • Busplot Viewer: Logic Analyzer now offers the Busplot Viewer capability for debugging DSP & RF applications. This allows users to plot different graphs based on the probe values vs. time or samples as well as other probes data. The Viewer lets user to select any signal to use as data for X and Y axis as well as plotting multiple graphs on the same plot.
  • HBM Monitor: New memory debug capability for monitoring HBM design status and performance. Similar to memory calibration debug, the HBM Monitor dashboard will show calibration status and static temperature of HBM memory modules along with various throughput information and monitor activity on different channels.
    
  • RF Analyzer: The RF Analyzer tool for debugging ZU+ RFSoC devices is now available. The tool is primarily used on user boards to help understand the performance of the board in high frequency applications. The RF Analyzer uses the same basic GUI as the RFSoC Evaluation Tool. While offering many similar features, RF Analyzer is board-independent. Without using specific board implementations information, RF Analyzer relies on BRAM buffers instead ofDDR RAM, requires users to configure an external PLL if the board requires so, and communicates via JTAG between the host PC and the target board.

• Intellectual Property (IP)

  • New 50G RS-FEC (544,514): New FEC (2x26G) NRZ used for 5G wireless applications to enable PAM-4 applications when adding an external bitmux chip
  • IntegratedUltraScale/UltraScale+ 100G Ethernet Subsystem: New optional AXI data bus interface allowing standard based interface
  • 10G/25G Ethernet Subsystem, 40G/50G Ethernet Subsystem, IntegratedUltraScale/UltraScale+100G Ethernet Subsystem, USXGMII, 1G/10G/25G Ethernet Switching Subsystem: Size optimized statistic counter by creating statistics logic based on features selected
  • Video and Imaging IPs: Video processing cores add support for 8K30 resolutions; Video mixer adds 16 layer mixing; Framebuffers adds support for 12 and 16bpc;
  • SmartConnect: Improved area efficiency, especially for small configurations and AXILite endpoints
  • AXI Bram Controller: Improved performance for single beat transactions. Configurable read latency for tight timing margins.

• Partial Reconfiguration

• Licenses for Partial Reconfiguration are no longer required for any Vivado Edition
  
  

Download Vivado Design Suite 2018.3 now, with support for:

• Virtex UltraScale+ 58G ES1 devices:- XCVU27P, XCVU29P
• Virtex UltraScale+ HBM: XCVU31P, XCVU33P, XCVU35P, XCVU37P
  
  
• Vivado Features:
  • QoR Improvements - 3% higher Fmax and 2x faster router compile times than 2018.1 (UltraScale+)
  • Easily compare report results across runs or run steps
  • New AXI-transaction based waveform viewer
  • Diff block diagrams for easier version control
  • Early timing closure analysis with Report QoR Analysis
            
• IP Subsystems/Cores:
  • Wireless: New 10G and 25G Radio over Ethernet Framer 
    • eCPRI Example Design
    • NGFI IEEE 1914.3 support
  • Wireless: New 25G Time Sensitive Networking (TSN) for 802.1CM
  • Wired: 400G, 200G, 100G and 50G Ethernet support for US+ 58G GTMs
  • HBM analysis cockpit available through HW debugger
  • Video IP: All HLS Video Processing cores are now license free and come installed with Vivado (VPSS, Video Mixer, Video TPG, Frame Buffer WR/RD, Gamma LUT, Demosaic, VTC.  Two new cores for Scene Change detection and Multi output scaler
     
• Embedded Software:
  • PetaLinux switch to standalone XSCT infrastructure
  • More robust multimedia infrastructure, including audio support
  • New license removes device restriction
  • Xen Hypervisor upgraded to Xen 4.11
  • Support for 64-bit memory addressing in MicroBlaze
• Production Devices:
  • Defense-Grade Zynq UltraScale+ RFSoC:- XQZU21DR (-1M), XQZU28DR (-1M, -1, -1LV, -1L, -2)
  • Defense-Grade Zynq UltraScale+ MPSoCs:- XQZU3EG( -1M, -1, -1LV, -1L, -2), XQZU9EG ( -1M, -1, -1LV, -1L, -2)