AMBA AXI4 (Advanced eXtensible Interface 4) is the fourth generation of the AMBA interface specification from ARM. AMD Vivado Design Suite 2014 and ISE Design Suite 14 extends the AMD platform design methodology with the semiconductor industry's first AXI4 Compliant Plug-and-Play IP.
For customers relying on IP to meet their Time-to-Market requirements for UltraScale™, 7 Series, Zynq™ 7000, Virtex™ 6 and Spartan™ 6 based designs, the AXI4 Plug-and-Play IP offers a single standard interface to make IP integration easier. AMD offers a broad set of AXI4 based IP with a single open standard interface across the Embedded, DSP, and Logic domains.
AMD worked closely with ARM to define the AXI4 specification for high-performance FPGA-based systems and designs. As part of our commitment to AXI4, AMD has adopted AXI4 as our next-generation IP interconnect standard for UltraScale, 7 Series, Zynq 7000, Spartan 6, Virtex 6 and future device families going forward
3rd party IP and EDA vendors everywhere have embraced the open AXI4 standard, helping to make it a widely adopted interface
AMD users will enjoy a wide range of benefits with the transition to AXI4 as a common user interface for IP. AXI4 is:
The AXI4 protocol is an update to AXI3 which is designed to enhance the performance and utilization of the interconnect when used by multiple masters. It includes the following enhancements:
AXI4-Lite is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interfaces are:
The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features of the protocol are: