Xilinx supports Full System Hardware Evaluation. The evaluation license key for this core will enable you to parameterize, generate and instantiate this IP in your design. It will also allow you to perform functional and timing simulation, generate a bitstream, and download and configure your design in hardware. The resulting IP will be fully functional in the FPGA for certain period of time, after which it will cease to function. To restore the evaluation core's operation in your design, simply reconfigure the FPGA with the bitstream.
Please refer to the Requirements link on the product page for this core for details on System Requirements for the Vivado and EDK configurations of this core.
Please note that the terms of the CAN LogiCORE IP Evaluation License Agreement apply toward your evaluation of this core.
Simulation Only Evaluation
Full System Hardware Evaluation
The procedures are the same as for the Simulation Only Evaluation, except that for the IP Catalog configuration of the core, you must additionally request and install a Full System Hardware Evaluation license key. This will allow you to generate a bitstream that you can use to program a Xilinx FPGA and evaluate the core in hardware for a limited amount of time.
IP Evaluation license keys in EDK are pre-programmed with a 14-month evaluation period which starts from the official release date of your particular version of EDK. You can generate EDK systems containing these Full System Hardware Evaluation cores throughout the 14-month evaluation period. When programmed into an FPGA, the evaluation cores will operate for certain period of time when running at the nominal clock frequency specified for the core.
To evaluate this core in EDK, simply:
After you purchase a license for the core, you will be able to generate a "Full" electronic license key for the latest released core version. Since the Full license key does not expire, installing it will enable you to generate new EDK systems containing the core version in question indefinitely. Systems containing the core generated with a Full license will not time out when programmed into an FPGA.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps: