Version Found: v1.2
Version Resolved and other Known Issues: See (Xilinx Answer 40469).
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
When targeting the VHDL flow, the generated core contains VHDL wrappers for the Integrated Block and AXI wrapper files, but not for the MGT wrapper files. The MGT wrappers are provided in Verilog.
This is expected behavior in the v1.2 core.
Revision History
12/06/2011 - Updated; added reference to (Xilinx Answer 40469)
10/21/2011 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 40469 | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| AR# 44682 | |
|---|---|
| Date | 08/26/2013 |
| Status | Active |
| Type | Known Issues |