AR# 46915


Zynq-7000 Debug - Setup the TRACE port via EMIO on the ZC702 board


This example design uses the FMC1 connector on the ZC702 board to attach the XILINX HW_FMC-105-DEBUG board. 

The TRACE port gets routed via EMIO to the mictor connector on the FMC-105.

Implementation Details

Design Type: PS and FPGA
Software Type: Standalone
PS Features: TRACE
PL Cores: ---
Boards/Tools: ZC702
Software Tools/Version: EDK 14.7

Other details:
Single core CPU @ 720MHz,FCLK (EMIOTRACECLK ) @ 200MHz, TRACECLK_pin @ 100MHz

Files Provided
Archived XPS project

Note: A version of the design built using Vivado IP Integrator is also attached.

In this AR we will:

  • Create a new Vivado project targeting the ZC702.
  • Source the .tcl to create the block design.
  • Add the constraints files.
  • Generate the output products.
  • Add the HDL wrapper (the attached wrapper is a workaround for (Xilinx Answer 60066)) and generate the bitstream.


In the design, FCLK_CLK0 is used to feed the EMIO port EMIOTRACECLK, and a divided by two version of FCLK_CLK0 is used to feed the external port TRACECLK_pin. 

This is because ARM defines two separate clocks, TRACECLKIN and TRACECLK, where TRACECLK = TRACECLKIN/2. 

TRACECLKIN is the input clock to the CoreSight components, and TRACECLK is the output clock that goes to the Lauterbach debugger. 

On EMIO, the EMIOTRACECLK port is actually TRACECLKIN. You will need to generate your own divide-by-2 version of this clock in the PL, and output it to the TRACECLK_pin.

Make sure that the EMIO TRACECLK is selected as the source clock for trace in the DBG_CLK_CTRL register; bit 6 of 0xF8000164 should be set to 1.

Step-by-step Instructions

  1. Connect the Platform Cable USB to J2
  2. Set SW10 to 10
  3. Use Impact to program the PL with the system.bit file generated by the attached design.
  4. Run XMD
  5. Connect arm hw
  6. Source ps7_init.tcl
  7. Call ps7_init 
Steps to set up the Vivado project:

  1. Create a blank Vivado project targeting the ZC702 board.
  2. Type cd {<full directory of ipi_design_20141.tcl >} in the Vivado Tcl console.
  3. Type source ipi_design_20141.tcl in the Vivado Tcl console.
  4. After block design creation has completed, generate the output products for the block design.
  5. After the product is generated, add the attached zynq_design_wrapper.v (this is a workaround for (Xilinx Answer 60066))
  6. Add the constraint files pjtag_constr.xdc and trace_constr.xdc to the Vivado project.
  7. Generate the bitstream. 
  8. After the bitstream is generated, open the implemented design.
  9. In the File menu, click Export Hardware for SDK, and check all selections.
  10. After SDK has launched, create fsbl and bsp.
  11. Open ps7_init.c in fsbl, and comment every line of EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x80000000U),.
  12. Save ps7_init.c, and compile fsbl again.
  13. Create a hello world application.
  14. You can generate BOOT.bin with the generated elf files of fsbl and hello world together with the bitstream.

Normally steps 11 and 12 are not needed if the PL is programed before running ps7_init.

This is due to the fsbl TPIU issue described in (Xilinx Answer 60755).

: We have several issues which have been worked around in the design ((Xilinx Answer 60901),(Xilinx Answer 60755),(Xilinx Answer 60066))

Note3: The Zynq-7 Processing Wizard 5.5 (2014.4) gives the TRACE_CLK_OUT signal as an output from the TPUI interface. 

This TPUI, TRACE_CLK_OUT output signal can be a user selectable source of a clock output. 

This TRACE_CLOCK_OUT clock can be used for TRACE_X port interface.

Expected Results

The TRACE port is functional.


Associated Attachments

Name File Size File Type 2 MB ZIP 54 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
50863 Zynq-7000 SoC - Debug N/A N/A

Associated Answer Records

AR# 46915
Date 11/13/2017
Status Active
Type General Article
Boards & Kits
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