AR# 51687


Design Advisory MIG 7 Series DDR3/DDR2 - Temperature monitor calibration using XADC block added to all DDR3/DDR2 designs in v1.7 (ISE 14.3/Vivado 2012.3)


Starting with the release of MIG v1.7, available with the ISE 14.3/Vivado 2012.3 design tools, the DDR3, DDR3L, and DDR2 designs include a temperature monitor system to maintain DQS center alignment in the read data window due to temperature variation/drift. This answer record is intended to supplement the information provided in the 7 Series FPGAs Memory Interface Solutions User Guide (AXI) (UG586) > DDR3 and DDR2 Memory Interface Solution > Core Architecture > PHY.

Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.



The temperature monitor calibration makes use of the 7 series XADC module. The MIG 7 series design instantiates the XADC block (within the "user_design/rtl/clocking/mig_7series_v1_x_tempmon.v" module) and handles polling at configurable intervals. 

The XADC outputs the current temperature which the MIG design then uses to update the alignment between DQS and the read data window if needed.

The RTL that reads the XADC temperature and makes adjustments as required is located in the "user_design/rtl/phy/mig_7series_v1_x_ddr_phy_tempmon.v" module. 

The memory controller sends an enable signal (tempmon_sample_en) to the mig_7series_v1_x_ddr_phy_tempmon.v module whenever a Refresh or ZQ Short Calibration has been sent to the DRAM and all pending transactions have cleared the DQ bus. 

The initial temperature read is performed to establish a baseline after the MIG 7 series calibration has completed. 

After each subsequent enable, the current temperature is compared to the baseline temperature. 

If the temperature change exceeds the threshold that triggers an update to the DQS to read window alignment, the module will adjust the PHASER_IN fine delay to mitigate temperature drift and sets a new baseline temperature. 

This process continues throughout normal operation. 

The XADC block is polled for the temperature every 10 microseconds and the memory controller performs any necessary updates during Refresh and ZQ Calibration.

The temperature monitor calibration is used across all supported frequencies. 

There is no impact or change to the performance specifications of the MIG 7 Series DDR3/DDR2 design as a result of these changes.

Designs Currently Not Using XADC

For designs currently not using the XADC block, version 1.7 of the MIG 7 series tool will automatically instantiate the XADC block in the memory controller design. Users simply need to ensure the XADC Instantiation option on the FPGA Options screen in MIG is set to Enabled, the default setting. Additionally, the requirements in the XADC Board Set-Up and MIG Usage section below must be met.

Designs Already Using XADC

There is only one XADC per 7 series device. For designs that already make use of the XADC block, the design can continue to use the block and supply the MIG 7 series code with the temperature periodically. The design's usage of the XADC must:

  • Within the XADC Wizard, the "Enable DRP" (Dynamic Reconfiguration Port) and "Enable DCLK" options must be enabled. These options enable the ability to sample the temperature. These are the only XADC options required by MIG 7 Series temperature monitor system. All other options should be set as required by the user design.
  • Include polling of the temperature from DADDR 7b0 every 1-10 microseconds.
  • The MSB 12 bits of the temperature read back during polling on DO[15:0] must then be supplied to the MIG core. The temperature can be input asynchronous to the MIG 7 series DDR3 IP.

Please review the 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide for specific information on XADC usage.

To disable the instantiation of the XADC within the generated MIG 7 series core, set the "XADC Instantiation" option to "Disabled." This option is available on the "FPGA Options" screen of the MIG 7 Series tool. Disabling the XADC instantiation will create a top-level input port "device_temp_i[11:0]. The 12 MSB bits of the "DO" DRP port need to be connected to this input port without any conversion. From Vivado 2014.1 onwards MIG supports supplying the temperature from 1 -116uS, as the XADC now has averaging enabled, previous versions used a refresh rate of 1 - 10 uS.

The Configuration of the XADC for MIG 2014.1 and forward is as follows:
    Continuous sequence mode with calibration enabled
    Enable calibration coefficients
    Averaging enabled for calibration
    Averaging =16 and enabled for temperature channel
    MIG config temperature measurement update time:  ~116us

NOTE: Disabling the instantiation of the XADC block through the MIG 7 series tool only allows users to keep their current usage of the block. It is not to disable usage of the temperature monitor calibration. The MIG 7 series DDR3/DDR2 designs require the XADC block and temperature monitor calibration to keep DQS centered in the read data window.

XADC Usage for DDRX Cores within EDK

The "XADC Instantiation" option within MIG 7 Series is not selectable when generating DDRX cores through EDK. Within the generated design, the instantiation of the XADC block is dependent on whether the top level device_temp_i input port is connected. Please see the 7 Series FPGAs Memory Interface Solutions User Guide (UG586) for complete details.

XADC Board Set-Up and MIG Usage

As long as all XADC specified guidelines have been followed, the MIG 7 series IP can make use of the block. MIG can either add the XADC or use one already in the design as long as the VREFP/N pins are connected with one of these XADC supported options:

  • Connected to external reference supply.
    NOTE: Vccadc must be powered appropriately. Please review the 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide.
  • Grounded through ferrite beads as specified in XADC.
    NOTE: Vccadc must be powered appropriately. Please review the 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide.
  • Directly grounded to board.
    NOTE: This option is ONLY feasible if the XADC is used exclusively for MIG. It is sufficient because of the accuracy required by the MIG temperature compensation. If VREFP/N and GNDADC are directly grounded on the board, Vccadc does not require power supply filtering and can be connected directly to Vccaux.

A Note for PHY Only Designs

The MIG 7 series Controller sends the enable to the mig_7series_v1_x_ddr_phy_tempmon.v module to read the temperature and, if needed, adjust the PHASER_IN fine delay. Designs using a custom controller are responsible for sending the enable. It is recommended to follow the same implementation as the MIG 7 series controller where the enable is sent during Refresh and ZQ Calibration. For full details on PHY only support and usage, see (Xilinx Answer 51204).

Additional Information

  • The temperature monitor system is used to maintain DQS center alignment in the read data window due to temperature variation/drift. This is separate from the dynamic alignment performed within the Phaser_IN which requires periodic reads during idle and long streams of write commands. The periodic reads are required to keep the Phaser_IN aligned and ready to properly capture during reads. For additional information, see (Xilinx Answer 43344).
  • For information on how to run a simulation that shows the temperature monitor circuit update the Phaser_IN taps based on a temperature change, see (Xilinx Answer 52523).

Revision History
04/16/2014 - Updated with MIG 2014.1 XADC Updates
03/06/2013 - Added EDK specific information
10/23/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51954 MIG 7 Series DDR2/DDR3 - PHY Initialization and Calibration N/A N/A

Associated Answer Records

AR# 51687
Date 04/15/2014
Status Active
Type Design Advisory
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