Version Found: MIG 7 Series v1.7
Version Resolved: See (Xilinx Answer 45195)
NOTE: THIS ANSWER RECORD AND THE INCLUDED PATCH HAS BEEN REPLACED BY (Xilinx Answer 53420). PLEASE VISIT THIS ANSWER RECORD.
The MIG 7 Series DDR3 core executes the OCLKDELAY calibration stage upon reset.
This stage moves the write DQS to the center of the write DQ data window.
An RTL issue has been found within this stage which affects designs with more than one DQS byte group.
The error causes the write DQS to be aligned to the write DQ. Potential failures are seen during the Write Calibration stage (wrcal_err=1).
This answer record describes the error and provides an RTL work-around.
The fix will be included in the v1.8 release of MIG 7 Series. All MIG 7 Series DDR3 designs need to include this update until v1.8 is available.
During OCLKDELAY calibration, the algorithm ensures edges found are not within jitter regions and, therefore, that false edges are not detected.
When the algorithm determines a found edge is legitimate, the signal "stable_eye_r" is asserted.
This signal must deassert before a new byte is calibrated so that the same false edge detection can be performed for each byte.
A new byte being calibrated is signified by an increment on cnt_dqs_r.
Due to the RTL issue, "stable_eye_r" remains asserted at the beginning of the next byte being calibrated, causing incorrect edge detection.
This results in Write Calibration errors or write window asymmetry where the write DQS is edge aligned (rather than center aligned) to the write DQ.
The ZIP file at the end of this answer record contains an updated "user_design/rtl/phy/mig_7series_v1_7_ddr_phy_oclkdelay_cal.v" module with instructions for how to include the file in the generated MIG 7 Series v1.7 design.
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