AR# 52847


Zynq-7000 Board Design - Sequencing for SRST and POR Signals


Zynq based boards should be laid out such that SRST and POR signals are asserted in a specific order.


Designers should ensure that the SRST signal is de-asserted before the POR signal is de-asserted when laying out Zynq-7000 boards.

This issue is related to (Xilinx Answer 52013).

Frequently Asked Questions About This Recommendation

Q1) Does this recommendation only affect initial power on?

A1) No, this also applies to reset sequences when the system is already up and running.

Q2) Can PS_SRST_B be pulled High if it is not used?

A2) Yes. Pulling PS_SRST_B High is the de-asserted state, so this would mean that it does not conflict with PS_POR_B.

Q3) Does this mean that PS_SRST_B cannot be asserted when PS_POR_B is asserted?

A3) No, PS_SRST_B can be asserted at the same time as PS_POR_B but PS_POR_B must be the last signal that is de-asserted.

Q4) How does this recommendation affect the release order of PS_SRST_B and PS_POR_B?

A4) PS_POR_B should be the last signal de-asserted and PS_SRST_B should not re-assert until after the BootROM is complete.

Q5) Does PS_SRST_B have to connect to an external sequencer/supervisor device?

A5) No, there is not a requirement to use a sequencer/supervisor, but it makes design easier and more straightforward. 

Managing this sequence can be done manually as long as the designer is careful to follow the recommendations above.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52539 Zynq-7000 SoC - Board Design N/A N/A

Associated Answer Records

AR# 52847
Date 04/25/2018
Status Active
Type General Article
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