AR# 63988: How to run timing simulation using Vivado Simulator?
How to run timing simulation using Vivado Simulator?
You can perform timing simulation after Synthesis or Implementation.
At the post-synthesis simulation stage, although it is not typical, you can perform timing simulation with estimated timing numbers.
At the post-implementation simulation stage, timing simulation is the closest emulation to actually downloading a design to a device.
It allows you to ensure that the implemented design meets functional and timing requirements and has the expected behavior in the device.
NOTE: Post-Synthesis and Post-Implementation timing simulations are supported for Verilog only.
There is no support for VHDL timing simulation.
This article describes the two ways to run timing simulation using Vivado Simulator: from the Vivado IDE and from the command line.
In the Vivado project, run Synthesis or Implementation.
Specify Vivado Simulator Simulation Settings if necessary.
From the Flow Navigator, select Run Simulation > Run Post-Synthesis Timing Simulation or Run Simulation > Run Post-Implementation Timing Simulation. The option becomes available only when synthesis or implementation is run successfully.
Run From Command Line:
Generate a Verilog timing simulation netlist for the design.