AR# 68310


UltraScale+ PCI Express Integrated Block (Vivado 2016.3) - Link training failure when "System Reset Polarity" is set to "active high"


Version Found: v1.1 Rev2 (Vivado 2016.3)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

The tactical patch provided with this answer record addresses link up issue when the "system reset polarity" option in configuration GUI is set  to "active high"

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express


This is a known issue to be fixed in a future release of the core, please install the tactical patch attached as described below:


  1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
  2. Extract the contents of the ".zip" archive to a directory starting with the name AR68310.
    Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
  3. Run Vivado software tools from the original install location.
  1. Create a separate directory for the patched files
  2. Extract the contents of the ".zip" archive to the desired patch directory location
  3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
    For example:
    set MYVIVADO=C:\MYVIVADO\vivado-patch-AR68310\vivado\
  4. Run Vivado software tools from the original install location.


Note: The "Version Found" column lists the version the problem was first discovered. 

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions. This is an issues with latency of the core.



Associated Attachments

Name File Size File Type 1 MB ZIP
AR# 68310
Date 10/04/2017
Status Active
Type Known Issues
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