AR# 68998

Description

The direct input GT reference clock coming from the IBUFDS might not be stable even after GTPOWERGOOD is asserted.

This condition causes two possible issues for IBERT:

Issue 1:

When generating IBERT designs that use the CPLL_CAL block (used with CPLL and internal system clocks), there could be an IBERT detection issue after the bitstream is downloaded into the device using Vivado hardware manager.

Issue 2:

The PLL might not lock for UltraScale GTY designs with a CPLL configuration when the quads used are not consecutive (for example, quads 225 and 227 are used, but not quad 226)

Solution

Issue 1 resolution:

Use a JTAG TCK frequency less than or equal to 6 MHz for IBERT designs that use both an internal system clock and CPLL.

Issue 2 resolution:

This applies to IBERT designs that use both an internal system clock, a CPLL, and non-consecutive quads.

Use a JTAG TCK frequency less than or equal to 6 MHz AND use a configuration with consecutive quads (for example, quads 225, 226, and 227) rather than non-consecutive.