AR# 71322

Reading AXI PCIe Gen3/XDMA internal registers using JTAG to AXI Master IP

Description

This answer record provides a method for reading AXI PCIe Gen3/XDMA internal registers using a JTAG to AXI Master IP in a downloadable PDF to enhance its usability.

Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

The document attached to this answer record describes the use of a JTAG to AXI Master IP to access the internal configuration registers through the AXI4-Lite interface of the AXI Bridge for PCI Express Gen3 (AXI PCIE Gen3) and the DMA Subsystem for PCI Express (XDMA).

A block diagram and Tcl commands have been provided to read and write to the internal registers and to probe the resulting AXI transactions in Vivado ILA.

The illustrated steps would be helpful for debugging by reading internal registers of the IP such as Interrupt Decode Register, Bridge Status and Control Register etc.

The method described would be particularly useful in situations where the processor hangs and the registers cannot be read from the software.

Revision History:

07/24/2018 - Initial release

Attachments

Associated Attachments

AR# 71322
Date 07/24/2018
Status Active
Type General Article
IP