AR# 71375

DMA Subsystem for PCI Express / Queue DMA subsystem for PCI Express (Vivado 2018.2) - Tactical patch for issue fixes

Description

Version Found:

  • DMA / Bridge Subsystem for PCI Express v4.1 - (Vivado 2018.2)
  • UltraScale+ PCI Express 4c Integrated Block v1.0 (Rev. 3) - (Vivado 2018.2)

Version Resolved and other Known Issues

The tactical patch provided with this answer record contains the following fixes for issues in the DMA / Bridge Subsystem for PCI Express in Vivado 2018.2.  

This patch contains all previously released fixes for the 2018.1 version, detailed in (Xilinx Answer 65443)

Issue 1:

The following property is set in the DMA / Bridge Subsystem for PCI Express (XDMA - DMA mode) IP for an UltraScale+ PCI Express 4c Integrated Block device:

set_property CONFIG.ext_sys_clk_bufg true [get_bd_cells <ip_name>]

The tool gives the following error:

Error message: [Synth 8-448] named port connection 'sys_clk_ce_out' does not exist for instance 'pcie4c_ip_i' of module 'pcie2axilite_sub_xdma_1_0_pcie4c_ip' ["/2018.2/test_designs/vu37p/freq_counters/freq_counters.srcs/sources_1/bd/pcie2axilite_sub/ip/pcie2axilite_sub_xdma_1_0/xdma_v4_1/hdl/verilog/pcie2axilite_sub_xdma_1_0_core_top.sv":4912]

sys_clk_ce_out is present at the XDMA IP level, but does not get propagated down to the pcie4c level.

The above issue also applies to the Queue DMA subsystem for PCI Express IP. 

The tactical patch provided with this answer record provides fixes for both the DMA Subsystem for PCI Express IP and the Queue DMA subsystem for PCI Express IP. 

Issue 2:

In Gen2 devices, the DMA / Bridge Subsystem for PCI Express v4.1 IP example design sends a corrupted MSI-X packet.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This issue will be fixed in the next release of the core. 

Please install the patch in Vivado 2018.2 as described in the readme file included in the patch zip file.

Note for Issue 1:

Instantiate BUFG_GT / BUFG_GT_SYNC external to the IP and IP Properties:

This fixes an issue where sharing sys_clk from the PCI Express IBUFDS_GTE4 between two or more components causes the design not to route.

This must be done prior to "Open Example Design". 

With this patch, after "Open Example Design" Steps 3 & 4 will be executed automatically.


1) In the DMA Subsystem for PCI Express or PCI Express Integrated Block, set the following property in the Vivado Tcl console:

  • For non-IP Integrator (non-Block Design) flow:
set_property CONFIG.ext_sys_clk_bufg true [get_ips <ip_name>]
  • For IP Integrator (Block Design) flow:
set_property CONFIG.ext_sys_clk_bufg true [get_bd_cells <ip_name>]

2) Reset Output Products on the IP or your Block Design and Regenerate Output Products again to have the new settings applied to the design.

3) Instantiate BUFG_GT and BUFG_GT_SYNC in your design as follows:

wire sys_clk_bufg;
wire sys_clk_ce_out;
wire sync_sc_ce;
wire sync_sc_clr.

BUFG_GT bufg_gt_sysclk (.CE (sync_sc_ce), .CEMASK (1'd0), .CLR (sync_sc_clr), .CLRMASK (1'd0), .DIV (3'd0), .I (sys_clk), .O (sys_clk_bufg));
BUFG_GT_SYNC sys_sys_clk (.CESYNC(sync_sc_ce), .CLRSYNC (sync_sc_clr), .CE(sys_clk_ce_out), .CLK(sys_clk), .CLR (1'b0));


4) Add/Replace the following ports in your DMA Subsystem for PCI Express or PCI Express Integrated Block IP instantiation:

.sys_clk ( sys_clk_bufg ),
.sys_clk_ce_out (sys_clk_ce_out)


Revision History:

08/02/2018Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR71375_Vivado_2018_2_preliminary_rev2.zip 11 MB ZIP
AR# 71375
Date 08/07/2018
Status Active
Type Known Issues
Devices
Tools
IP