Sharing the sys_clk from the PCI Express IBUFDS_GTE4 between two or more components is causes routing issues.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
Follow the steps below to support clock sharing in Vivado 2017.4 and newer Vivado versions.
Note: If you are using the example design, make sure Step 1 and Step 2 are done prior to Opening the IP Example Design.
The example design will automatically be populated with Step 3 and Step 4, so it is not required to execute those steps.
set_property CONFIG.ext_sys_clk_bufg true [get_ips <ip_name>]
set_property CONFIG.ext_sys_clk_bufg true [get_bd_cells <ip_name>]
2) Reset Output Products on the IP or your Block Design, and Regenerate Output Products to have the new settings applied to the design.
3) Instantiate BUFG_GT and BUFG_GT_SYNC in your design as follows:
02/27/2019 - Initial Release