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AR# 71730

DMA / Bridge Subsystem for PCI Express and UltraScale+ PCI Express Integrated Block (Vivado 2017.4) - Clock Sharing with sys_clk requirements

Description

Sharing the sys_clk from the PCI Express IBUFDS_GTE4 between two or more components is causes routing issues.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

Follow the steps below to support clock sharing in Vivado 2017.4 and newer Vivado versions.

Note: If you are using the example design, make sure Step 1 and Step 2 are done prior to Opening the IP Example Design.

The example design will automatically be populated with Step 3 and Step 4, so it is not required to execute those steps.


1) In the DMA Subsystem for PCI Express or PCI Express Integrated Block, set the following property in the Vivado Tcl console:

  • Non IP Integrator (non-Block Design) flow:
set_property CONFIG.ext_sys_clk_bufg true [get_ips <ip_name>]
  • IP Integrator (Block Design) flow:
set_property CONFIG.ext_sys_clk_bufg true [get_bd_cells <ip_name>]

2) Reset Output Products on the IP or your Block Design, and Regenerate Output Products to have the new settings applied to the design.

3) Instantiate BUFG_GT and BUFG_GT_SYNC in your design as follows:


wire sys_clk_bufg;
wire sys_clk_ce_out;
wire sync_sc_ce;
wire sync_sc_clr.

BUFG_GT bufg_gt_sysclk (.CE (sync_sc_ce), .CEMASK (1'd0), .CLR (sync_sc_clr), .CLRMASK (1'd0), .DIV (3'd0), .I (sys_clk), .O (sys_clk_bufg));
BUFG_GT_SYNC sys_sys_clk (.CESYNC(sync_sc_ce), .CLRSYNC (sync_sc_clr), .CE(sys_clk_ce_out), .CLK(sys_clk), .CLR (1'b0));


4) Add/Replace the following ports in your DMA Subsystem for PCI Express or PCI Express Integrated Block IP instantiation:

.sys_clk ( sys_clk_bufg ),
.sys_clk_ce_out (sys_clk_ce_out)

Revision History:

02/27/2019 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34536 Xilinx Solution Center for PCI Express N/A N/A
AR# 71730
Date 02/28/2019
Status Active
Type General Article
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IP
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