Version Found: 2019.2
When the IP cores listed below are configured with the following options, CPLL fails to clock:
The following IP cores are affected:
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
This a known issue to be fixed in a future version of the core.
The patch attached to this Answer Records contains a "readme" file which includes installation instructions.
Please install the patches for your corresponding version of Vivado.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.
|Name||File Size||File Type|