AR# 73417

PCI Express Integrated Block (Vivado 2019.2) - CPLL fails to lock in when reference clock is set to 250MHz at Gen1 rate

Description

Version Found: 2019.2

When the IP cores listed below are configured with the following options, CPLL fails to clock:

  • Maximum link speed: 2.5Gbps
  • Reference clock frequency: 250MHz
  • GT DRP clock selection: Internal

The following IP cores are affected:

  • UltraScale+ PCI Express Integrated Block
  • UltraScale+ PCI Express 4c Integrated Block
  • DMA Subsystem for PCI Express
  • Queue DMA subsystem for PCI Express 

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This a known issue to be fixed in a future version of the core.

The patch attached to this Answer Records contains a "readme" file which includes installation instructions.

Please install the patches for your corresponding version of Vivado.

 

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

  • 03/26/2020 - Initial Release
  • 06/13/2020 - Patch Update (Rev2)

Attachments

Associated Attachments

Name File Size File Type
AR73417_Vivado_2019_2_preliminary_rev2.zip 22 MB ZIP
AR# 73417
Date 06/27/2020
Status Active
Type General Article
Devices More Less
IP More Less