6 steps to setup and accelerate your application using Vitis Unified Software Platform:
Develop accelerated applications with the Vitis Unified Software Platform in the Cloud – No local software installations or upfront purchase of hardware platforms necessary (pay-as-you-go). Log in and get started right away.
In this webinar, learn about the Vitis environment and how it enables the development of embedded software and accelerated applications on Xilinx platforms.
See how Vitis unifies software, acceleration, and ML development under a single development platform.
The Vitis™ unified software platform documentation provides support for using Vitis for each of the two software development flows: Application acceleration development and Embedded software development.
|Introduction to the Vitis™ Unified Software Platform||Explains how software/hardware engineers and application developers can benefit from the Vitis unified software environment and OpenCL framework.|
|Vitis IDE Tool Overview||Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code.|
|Vitis Command Line Flow||Introduces the Vitis environment makefile flow where the user manages the compilation of host code and kernels.|
|Vitis Accelerated Libraries||Describes the Vitis accelerated libraries that are available for domain-specific and common libraries. These libraries are open-source, performance-optimized libraries that offer out-of-the-box acceleration.|
|Creating a Vitis Embedded Acceleration Platform (Edge)||Describes the Vitis embedded acceleration platform, which provides product developers an environment for creating embedded software and accelerated applications on heterogeneous platforms based on FPGAs, Zynq SoCs, and Alveo data center cards.|
|Overview of the Versal ACAP Architecture||Provides an overview of the Versal architecture at a high level and describes the various engines in the Versal ACAP, such as the Scalar Engines, Adaptable Engines, and Intelligent Engines. Also describes how the AI Engine in the Versal ACAP meets many dynamic market needs.|
|Introduction to the Versal AI Engine Architecture||Introduces the architecture of the AI Engine and describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces.|
|Versal AI Engine Memory and Data Movement||Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays.|
|Versal ACAP Tool Flow||Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform.|
|Application Partitioning on Versal ACAPs 1||Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP.|
|The Programming Model: Single Kernel||Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program using the Vitis IDE tool.|
|The Programming Model: Introduction to the Adaptive Data Flow (ADF) Graph||Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports.|
Looking for additional on-demand training courses? As a member of the developer program, you also receive a 50% discount on select courses!
1. Log into https://lmstraining.xilinx.com with your Xilinx developer account
2. Search Developers Program in the search box to populate the discounted courses
3. Purchase and get started
|Accelerating Applications with the Vitis Unified Software Environment
||Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications.|
|Designing with Versal AI Engine 1 - Architecture and Design Flow||This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to analyze the kernel program using various debugger features.|
|Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels||
This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine.
Visit the Xilinx Customer Training Center for additional paid courses
Learn how developers are using Xilinx technologies to accelerate their work. Learn from the tutorials, articles, and projects from the community.
Share your work (Github repo, Hackster.io link etc) with us at firstname.lastname@example.org and every month we will select projects to be featured on our developer site. Projects with be based on design features, performance, creativity, and originality.
Joining the Xilinx Developer program gives you access to the resources necessary to build your applications successfully on all Xilinx platforms. Benefits of your membership include: Access to free training courses on Xilinx tools and platforms, Opportunities to showcase your projects and articles on the Xilinx Developer site, and much more!