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  3. Error Correction Checking (ECC) Core

Error Correction Checking (ECC) Core

Overview

Product Description

The LogiCORE™ IP ECC core is ideal for robust data transmission with error correction and checking capabilities. The adaptable core supports Hamming and Hsiao algorithms for Single Error Correction and Double Error Detection (SEC-DED) error correction codes (ECC). The ECC core supports data widths between 4 and 128 bits and can be used with internal and external memories and with high speed Multi Gigabit transceivers.

Key Features and Benefits

  • Supports Single Bit Error correction and double bit error detection functions
  • Supports hamming algorithm for 4 to 64 data widths
  • Supports Hsiao algorithm for 4 to 128 data widths
  • Supports encode only, decode only and encode/decode modes
  • Supports clock enable and synchronous active high reset
  • Provides option to add input/output registering stages
  • Provides optional internal pipelining stage for high frequency operations
  • Supports dynamically enabling or disabling error correction function
  • Provides Single Bit Error corrected and two bit error detected status outputs

Support

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Documentation

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