Xilinx® offers the 100 Gigabit IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the IEEE 802.3bj-2014 specification and connects seamlessly to the Xilinx integrated or soft 100G Ethernet MAC IP on Virtex® UltraScale™.
Key Features and Benefits
Supports RS(528,514) KR4 and RS(544,514) KP4
Supports 100 Gigabits
Configuration and status bus
Selectable AXI4-Lite interface for status output
Transcode Bypass mode for direct access to RS-FEC encoder/decoder
Example reference design demonstrating integrated 100G Ethernet IP with RS-FEC