The Vitis™ HLS tool allows users to easily create complex FPGA algorithms by synthesizing a C/C++ function into RTL. The Vitis HLS tool is tightly integrated with both the Vivado™ Design Suite for synthesis and place & route and the Vitis™ unified software platform for heterogenous system designs and applications.
Vitis™ HLS C code is geared towards taking advantage of the benefits and characteristics offered by the architecture of AMD FPGAs.
The Vitis HLS tool supports parallel programming constructs in order to model a desired implementation. These constructs include:
The Vitis HLS tool synthesizes different parts of C code differently:
C to RTL Synthesis
Simulation and Verification
The Vitis HLS tool has built-in simulation flows to enable faster verification times:
The output of the Vitis HLS tool is an RTL implementation that can be either packaged into a compiled object file (.xo) or exported to an RTL IP:
*The benchmark tests were performed on all 1208 Vitis L1 library C-code designs as of February 12th, 2023. All designs were run using a system with 2P Intel Xeon E5-2690 CPUs with CentOS Linux, SMT enabled, Turbo Boost disabled. Hardware configuration not expected to effect software test results. Results may vary based on software and firmware settings and configurations- VGL-03