Soft Error Mitigation (SEM) IP cores perform SEU detection, correction, and classification for configuration memory. The cores utilize device primitives such as ICAP and FRAME_ECC to clock and observe the Readback CRC feature as part of the SEU detection function. For SEU correction, the IP cores perform the necessary operations to locate and correct errors. For SEU classification, the IP cores use AMD Essential Bits technology to further increase system availability.
The SEM IP cores also perform emulation of SEUs by injecting errors into configuration memory. The error injection feature provides a means to evaluate and test the SEU mitigation capabilities of the IP cores without the need for expensive test time at a radiation effects facility.