Xilinx 3D ICs utilize stacked silicon interconnect (SSI) technology to break through the limitations of Moore’s law and deliver the capabilities to satisfy the most demanding design requirements. Xilinx homogeneous and heterogeneous 3D ICs deliver the highest logic density, bandwidth, and on-chip resources in the industry, breaking new ground in system-level integration.
Xilinx UltraScale™ 3D ICs provide unprecedented levels of system integration, performance, bandwidth, and capability. Both Virtex® UltraScale 3D ICs and Kintex® UltraScale 3D ICs contain a step-function increase in both the amount of connectivity resources and the associated inter-die bandwidth in this second-generation 3D IC architecture. The big increase in routing and bandwidth and the new 3D IC wide memory optimized interface ensures that next-generation applications can achieve their target performance at extreme levels of utilization. Virtex UltraScale+ 3D ICs include all of the architectural innovations delivered with the UltraScale families and incorporate 16nm 3D transistors for a “3D-on-3D” step function increase in performance per watt, with optional HBM memory.
SSI technology is well established being used in Versal™ HBM series, Versal Premium series, Virtex UltraScale+, Virtex UltraScale, Kintex UltraScale, and Virtex-7 families – thereby offering customers a broad range of resources and capabilities to match leading edge demands. The SSI devices shown below offer unprecedented FPGA capabilities and are ideal for applications such as next-generation wired communications, high-performance computing, medical image processing, and ASIC prototyping/emulation.
|Xilinx 3D IC Devices|
Xilinx 3D IC devices utilize SSI technology, enabling high-bandwidth connectivity between multiple die and provide massive inter-die bandwidth-per-watt compared to multi-chip approaches.The devices consume lower power while enabling the integration of transceivers and on-chip resources within a single package. SSI technology leverages proven microbump technology combined with coarse pitch through-silicon vias (TSVs) on a passive (no transistors) 65 nm silicon interposer to deliver high reliability interconnect without performance degradation on one FPGA device. This breakthrough technology provides the next level of advanced system integration for applications that require high logic density and tremendous computational performance.