Power Efficiency

Unrivaled System-level Power Reduction

Overview

Through careful selection of silicon process and power-conscious architecture design, Xilinx devices deliver power efficiency across all product portfolios, including Spartan-6, 7 series, UltraScale™, and UltraScale+™ FPGAs, SoCs and ACAPs. With each generation, Xilinx broadens its power reduction capabilities, ranging from process enhancements, architectural innovations, aggressive voltage scaling strategies, and advanced software optimization strategies. More detail on portfolio-specific capabilities, silicon process advantages, and benchmark comparisons are shown below. Power estimation, thermal models, full software support, and demonstration boards are publicly available for all families. Designing power for Xilinx devices is easier than ever before with comprehensive documentation, built & tested power reference designs and powerful tools to unlock the potential of your next design to get the most out of your ACAP, SoC, or FPGA.

Versal ACAP

Xilinx’s next generation heterogeneous compute device, Versal ACAP (Adaptive Compute Acceleration Platform), based on TSMCs 7nm HK-MG FinFET process, takes the next leap in low power and high-performance technology through architectural innovation and power optimized blocks. Versal’s AI Engine architecture allows for up to 40% power savings for compute intensive applications while significantly increasing performance over traditional FPGA implementation.

  • Hardened BRAM, URAM and DSP blocks improve device efficiency:
  • More efficient DSP blocks for enhanced complex and floating-point math operations
  • Unused Block RAMs support power gating to avoid leakage power
  • URAM Initialization and width configurability reduce the need for external RAM/ROM

The combination of hardened and programmable blocks allows Versal ACAP to maximize performance per Watt along with previous generations power savings, improved power management, new Voltage and frequency scaling and integrated System Monitor enables intelligent power management for your board and only consume power when necessary.
 

UltraScale+ FPGAs

Based on a high performance, low-power semiconductor process (TSMC 16nm FinFET+), the UltraScale+ device families delivers up to 60% overall device-level power savings over 7 series FPGAs and SoCs. Architectural enhancements include:

  • Hardware-based clock gating
  • Hardened BRAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers

Through architectural innovation and a dual-voltage operation of the primary core fabric, UltraScale+ families more than double the performance-per watt-capabilities of 7 series families by realizing power reductions while improving overall performance.

  7 Series
(28nm)
VNOM
UltraScale
(20nm)
VNOM
UltraScale+
(16nm)
VNOM
UltraScale+
(16nm)
VLOW
Operating Voltage (VCCINT) 1V 0.95V 0.85V 0.72V
Normalized Facric Performance 1.0x 1.2x 1.6x 1.2x
Normalized Total Power 1.0x 0.7x 0.8x 0.5x
Performance/Watt 1.0x 1.7x 2x 2.4x

Zynq UltraScale+ MPSoCs

In addition to all the power reducing capabilities of UltraScale+ FPGA logic, Zynq UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands, lowering overall device power.

UltraScale FPGAs

Based on a low-power 20nm semiconductor process coupled with significant static and power gating, UltraScale FPGA families deliver up to 40% overall device-level power savings compared to 7 series FPGAs. Architectural enhancements shared with UltraScale+ devices include

  • Hardware-based clock gating
  • Hardened BRAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers
  7 Series
(28nm)
VNOM
UltraScale
(20nm)
VNOM
UltraScale+
(16nm)
VNOM
UltraScale+
(16nm)
VLOW
Operating Voltage (VCCINT) 1V 0.95V 0.85V 0.72V
Normalized Facric Performance 1.0x 1.2x 1.6x 1.2x
Normalized Total Power 1.0x 0.7x 0.8x 0.5x
Performance/Watt 1.0x 1.7x 2x 2.4x

7 Series FPGAs & Zynq-7000 Programmable SoCs

As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices offer up to 50% total power reduction over previous generation families and superior performance per watt compared to competing 28nm solutions. Architectural and block-level innovations include:

  • Dynamic Function eXchange for static power savings
  • Multi-mode I/O control
  • Intelligent clock gating
  • Power binning and voltage scaling

View competitive benchmark summaries as well as detailed benchmark process.

Power Delivery Solutions

Optimized Power Delivery Solutions

Power management requirements are diverse and often unique to a specific use case. As a result, no single power management design can provide the optimal solution. Xilinx partners with the industry’s leading power management companies (list below) to provide a variety of reference designs mapping to common use cases, as well as overall guidance on the power supply requirements of Xilinx products  

Reference Designs

Below you will find a selection of reference designs developed together with some of our power management partners. Designs are grouped by product family, however, many of these reference designs can be easily modified and applied to other product families. Please contact our partners for additional information and guidance in relation to any designs shown below.

Vendor Reference Design ACAP Series Target Device
Infineon EV-121-D AI Core, Prime VC1902,
VM1802
Intersil-Renesas VERSALDEMOZ1 AI Core, Prime VC1902,
VM1802
Analog Devices, Inc Contact ADI
AI Core, Prime VC1902,
VM1802
Maxim Integrated MAXREFDES1238   AI Core, Prime VC1902,
VM1802
Monolithic Power Systems EVREF105A AI Core, Prime VC1902,
VM1802
Size Optimized EVXLVA_02-A AI Core, Prime VC1902,
VM1802
Texas Instruments
Coming Soon
AI Core, Prime VC1902,
VM1802
Hardware Verified Reference Designs
Vendor Reference Design Target Device(s) Analog Rails
Infineon Xilinx ZCU111 Eval Board ZU21 -ZU29 LDOs
Monolithic Power Systems EVREF0102A - RFSoC Analog Power Module Board
ZU21 - ZU29 Switching Regulators -Modules
Intersil-Renesas  ISL8024DEMO2Z - RFSoC Analog Power Module Board ZU21 - ZU29 Switching Regulators - Discrete
Non-Hardware Verified Reference Designs
Vendor Reference Design Target Device(s) Analog Rails
Monolithic Power Systems
Size Optimized Solution using Power Modules
ZU21 - ZU29 Switching Regulators -Modules
Highly Integrated Solution with Internal Sequencing ZU21 - ZU29 Switching Regulators -Modules
Size & Efficiency Optimized Power Solutions with PMBus ZU21 - ZU29 Switching Regulators -Modules

Note 1: For more information on Zynq UltraScale+ device use-cases, please see the Power Supply Consolidation Solutions for Zynq UltraScale+ MPSoCs section of  UG583.

Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
Intersil/Renesas Xilinx VCU128 Eval Board Virtex UltraScale+ VU37P/VU19P1
Monolithic Power Systems Area optimised module based solution for Kintex UltraScale+ Kintex UltraScale+ All KU+
High Power Density Discrete Solution Virtex UltraScale+ VU19P-VU57P
Fully Integrated Solution Using Modules Virtex UltraScale+ VU19P-VU57P
ABB Scalable module based solution for Virtex UltraScale+ Virtex UltraScale+ VU37P
Cyntec

Scalable module based solution for Virtex UltraScale+

Virtex UltraScale+

VU37P

Non-Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
Monolithic Power Systems Efficiency Optimised Power Delivery Solution Virtex UltraScale+ VU3P-VU13P, VU31P-VU37P
Size Optimised Power Delivery Solution Virtex UltraScale+ VU3P-VU13P, VU31P-VU37P
Size or Efficiency Optimised Power Delivery Solution Virtex UltraScale+ VU19P, VU27P/29P, VU47P/49P, VU57P
Integrated Sequencing Power Delivery Solution Kintex UltraScale+ KU3P-KU15P
Size Optimised Power Delivery Solution Kintex UltraScale+ KU3P-KU15P
Hardware Verified Reference Designs
Non-Hardware Verified Reference Designs
Vendor Reference Design Product Family Target Device(s)
Monolithic Power Systems Size Optimized Power Module Solution with Scalable VCCINT Kintex UltraScale KU025-KU115

Note: All solutions are the responsibility of the specific power vendor. Please check with the appropriate power vendor for additional information, e.g., availability.

Webinars and App Notes

Power Management Companies

Distribution Partner

Thermal

Thermal Design:

Understating the thermal design limits of an application varies greatly between application types and end markets, a lower power design at a high ambient can experience the same thermal challenges as a high power design at a much lower ambient and so understanding what the limits of a system are is critical for both a successful product and a cost effective product, as overdesign a thermal solution incurs extra cost and complexity to a design.

To this end Xilinx provides DELPHI thermal models for all of current devices, these support both Siemens Flotherm and Ansys IcePak.

*Versal ACAP Models (Coming Soon)

Xilinx U280 airflow & heatmap simulation
Xilinx U280 airflow & heatmap simulation
Xilinx U50 heatmap simulation
Xilinx U50 heatmap simulation

Thermal simulation is a critical step in board design and as indicated in the board methodology process chart, the results of the initial estimation should be used for the thermal solution validation.

board-methodology-process-chart

Thermal Design Partners

Not all customers have access to either the thermal simulation tools or the resources to run a thermal simulation, through the Xilinx Alliance program you can access partners that have Thermal design capability.

Package selection

An important part of device selection is selecting the right package for a successful thermal design. Xilinx devices are available is many package types to cater for different customers requirements, however from a thermal standpoint the Lidless packaging offers the best thermal performance, Xilinx devices are offered in the following packages:


Bare Die – Package Designator (SB/VB)

  • "B" indicates Bare Die, S for 0.8mm & V for 0.92mm package pitch

Lidded -  (SF/VF)

  • "F" For Forged Lid, S for 0.8mm & V for 0.92mm package pitch

Lidless Package (VS/LS)

  • "S" indicated the Stiffener Ring, V for 0.92mm & L for 1mm pitch
  • Provides optimal Thermal Performance


Lidless Overhang Package (VI)

  • "I" indicates a stiffener ring with package overhead (package substrate larger than the BGA footprint)
  • "V" indicates 0.92mm package pitch
  • Provides optimal Thermal Performance
Documentation

Documentation

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Tools

Power Efficiency

Xilinx provides best-in-class tools to estimate pre-implementation power consumption, optimize for lowest power at every design stage, and provide extensive analysis for user-guided optimization. Below are a variety of power-related and Xilinx industry-leading hardware and software-based tools for designers to get started today.

Training & Support
Video

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