Power Efficiency

Through careful selection of silicon process and power-conscious architecture design, Xilinx devices deliver power efficiency across all product portfolios, including Spartan-6, 7 series, UltraScale™, and UltraScale+™ FPGAs, SoCs and ACAPs. With each generation, Xilinx broadens its power reduction capabilities, ranging from process enhancements, architectural innovations, aggressive voltage scaling strategies, and advanced software optimization strategies. More detail on portfolio-specific capabilities, silicon process advantages, and benchmark comparisons are shown below. Power estimation, thermal models, full software support, and demonstration boards are publicly available for all families. Designing power for Xilinx devices is easier than ever before with comprehensive documentation, built & tested power reference designs and powerful tools to unlock the potential of your next design to get the most out of your ACAP, SoC, or FPGA.

Xilinx’s next generation heterogeneous compute device, Versal ACAP (Adaptive Compute Acceleration Platform), based on TSMCs 7nm HK-MG FinFET process, takes the next leap in low power and high-performance technology through architectural innovation and power optimized blocks. Versal’s AI Engine architecture allows for up to 40% power savings for compute intensive applications while significantly increasing performance over traditional FPGA implementation.

• Hardened BRAM, URAM and DSP blocks improve device efficiency:
• More efficient DSP blocks for enhanced complex and floating-point math operations
• Unused Block RAMs support power gating to avoid leakage power
• URAM Initialization and width configurability reduce the need for external RAM/ROM

The combination of hardened and programmable blocks allows Versal ACAP to maximize performance per Watt along with previous generations power savings, improved power management, new Voltage and frequency scaling and integrated System Monitor enables intelligent power management for your board and only consume power when necessary.
 

Based on a high performance, low-power semiconductor process (TSMC 16nm FinFET+), the UltraScale+ device families delivers up to 60% overall device-level power savings over 7 series FPGAs and SoCs. Architectural enhancements include:

• Hardware-based clock gating
• Hardened BRAM cascading
• DSP block efficiencies
• Power-optimized transceivers

Through architectural innovation and a dual-voltage operation of the primary core fabric, UltraScale+ families more than double the performance-per watt-capabilities of 7 series families by realizing power reductions while improving overall performance.

In addition to all the power reducing capabilities of UltraScale+ FPGA logic, Zynq UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands, lowering overall device power.

Based on a low-power 20nm semiconductor process coupled with significant static and power gating, UltraScale FPGA families deliver up to 40% overall device-level power savings compared to 7 series FPGAs. Architectural enhancements shared with UltraScale+ devices include

• Hardware-based clock gating
• Hardened BRAM cascading
• DSP block efficiencies
• Power-optimized transceivers

As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices offer up to 50% total power reduction over previous generation families and superior performance per watt compared to competing 28nm solutions. Architectural and block-level innovations include:

• Dynamic Function eXchange for static power savings
• Multi-mode I/O control
• Intelligent clock gating
• Power binning and voltage scaling

View competitive benchmark summaries as well as detailed benchmark process.