Power Efficiency

Through careful selection of silicon process and power-conscious architecture design, AMD devices deliver power efficiency across all product portfolios, including adaptive compute acceleration platform (ACAP) devices, Spartan™ 6 FPGAs, 7 series FPGAs, UltraScale™ FPGAs, UltraScale+™ FPGAs, and adaptive SoCs. With each generation, AMD broadens its power-reduction capabilities, ranging from process enhancements, architectural innovations, aggressive voltage scaling, and advanced software optimization strategies. More details on portfolio-specific capabilities, silicon process advantages, and benchmark comparisons are shown below. Power estimation, thermal models, full software support, and demonstration boards are publicly available for all families. Designing power for AMD devices is easier than ever before with comprehensive documentation, built and tested power reference designs, and powerful tools to unlock the potential of your next design to get the most out of your ACAP, SoC, or FPGA.

The Versal™ ACAP is the next-generation, heterogeneous compute device built on TSMC’s 7nm HK-MG FinFET process, taking the next leap in low-power and high-performance technology through architectural innovation and power-optimized blocks. The Versal AI Engine architecture delivers up to 40% power savings for compute-intensive 

• Hardened block RAM, UltraRAM, and DSP blocks improve device efficiency
• More efficient DSP blocks for enhanced complex and floating-point math operations
• Unused block RAMs support power gating to avoid power leakage
• UltraRAM initialization and width configurability reduce the need for external RAM/ROM

The combination of Versal ACAP hardened and programmable blocks allows designers to maximize performance per watt by including previous generation power-saving techniques, as well as improved power management, new voltage and frequency scaling, and integrated system monitoring for board-level, intelligent power management.

Built on TSMC’s 16nm FinFET+ high-performance, low-power semiconductor process, the UltraScale+ device families deliver up to 60% overall device-level power savings over 7 series FPGAs and SoCs. Architectural enhancements include:

• Hardware-based clock gating
• Hardened block RAM cascading
• DSP block efficiencies
• Power-optimized transceivers

Through architectural innovation and dual-voltage operation of the primary core fabric, UltraScale+ families more than double the performance per watt capabilities of 7 series families by realizing power reductions while improving overall performance.

UltraScale+ FPGA power savings

In addition to all the power reducing capabilities of UltraScale+ FPGA logic, Zynq™ UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands—lowering overall device power.

Built on TSMC’s low-power 20nm semiconductor process coupled with significant static and power gating, UltraScale FPGA families deliver up to 40% overall device-level power savings compared to 7 series FPGAs. Architectural enhancements shared with UltraScale+ devices include:

• Hardware-based clock gating
• Hardened block RAM cascading
• DSP block efficiencies
• Power-optimized transceivers

UltraScale power savings

As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices and Zynq 7000 SoCs offer up to 50% total power reduction over previous generation families and superior performance per watt compared to competing 28nm solutions. Architectural and block-level innovations include:

• Dynamic Function eXchange (DFX) for static power savings
• Multi-mode I/O control
• Intelligent clock gating
• Power binning and voltage scaling

View competitive benchmark summaries as well as detailed benchmark process.